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 ICX418AKB
Diagonal 8mm (Type 1/2) CCD Image Sensor for NTSC Color Video Cameras
Description The ICX418AKB is an interline CCD solid-state image sensor suitable for NTSC color video cameras with a diagonal 8mm (Type 1/2) system. Compared with the current product ICX038DNB, basic characteristics such as sensitivity, smear, dynamic range and S/N are improved drastically. This chip features a field period readout system and an electronic shutter with variable charge-storage time. Also, this outline is miniaturized by using original package. This chip is compatible with the pins of the ICX038DNB and has the same drive conditions. 16 pin DIP (Ceramic)
Pin 1 2
V
Features * High sensitivity (+6.0dB compared with the ICX038DNB) 3 * Low smear (-5.0dB compared with the ICX038DNB) 40 H Pin 9 * High D range (+2.0dB compared with the ICX038DNB) * High S/N Optical black position * High resolution and low dark current (Top View) * Excellent antiblooming characteristics * Ye, Cy, Mg, and G complementary color mosaic filters on chip * Continuous variable-speed shutter * Substrate bias: Adjustment free (external adjustment also possible with 6 to 14V) * Reset gate pulse: 5Vp-p adjustment free (drive also possible with 0 to 9V) * Horizontal register: 5V drive * Maximum package dimensions: 13.2mm Device Structure * Interline CCD image sensor * Optical size: Diagonal 8mm (Type 1/2) * Number of effective pixels: 768 (H) x 494 (V) approx. 380K pixels * Total number of pixels: 811 (H) x 508 (V) approx. 410K pixels * Chip size: 7.40mm (H) x 5.95mm (V) * Unit cell size: 8.4m (H) x 9.8m (V) * Optical black: Horizontal (H) direction: Front 3 pixels, rear 40 pixels Vertical (V) direction: Front 12 pixels, rear 2 pixels * Number of dummy bits: Horizontal 22 Vertical 1 (even fields only) * Substrate material: Silicon
12
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
-1-
E01907A41
ICX418AKB
USE RESTRICTION NOTICE (December 1, 2003 ver.) This USE RESTRICTION NOTICE ("Notice") is for customers who are considering or currently using the CCD products ("Products") set forth in this specifications book. Sony Corporation ("Sony") may, at any time, modify this Notice which will be available to you in the latest specifications book for the Products. You should abide by the latest version of this Notice. If a Sony subsidiary or distributor has its own use restriction notice on the Products, such a use restriction notice will additionally apply between you and the subsidiary or distributor. You should consult a sales representative of the subsidiary or distributor of Sony on such a use restriction notice when you consider using the Products. Use Restrictions * The Products are intended for incorporation into such general electronic equipment as office products, communication products, measurement products, and home electronics products in accordance with the terms and conditions set forth in this specifications book and otherwise notified by Sony from time to time. * You should not use the Products for critical applications which may pose a life- or injury- threatening risk or are highly likely to cause significant property damage in the event of failure of the Products. You should consult your Sony sales representative beforehand when you consider using the Products for such critical applications. In addition, you should not use the Products in weapon or military equipment. * Sony disclaims and does not assume any liability and damages arising out of misuse, improper use, modification, use of the Products for the above-mentioned critical applications, weapon and military equipment, or any deviation from the requirements set forth in this specifications book. Design for Safety * Sony is making continuous efforts to further improve the quality and reliability of the Products; however, failure of a certain percentage of the Products is inevitable. Therefore, you should take sufficient care to ensure the safe design of your products such as component redundancy, anti-conflagration features, and features to prevent mis-operation in order to avoid accidents resulting in injury or death, fire or other social damage as a result of such failure. Export Control * If the Products are controlled items under the export control laws or regulations of various countries, approval may be required for the export of the Products under the said laws or regulations. You should be responsible for compliance with the said laws or regulations. No License Implied * The technical information shown in this specifications book is for your reference purposes only. The availability of this specifications book shall not be construed as giving any indication that Sony and its licensors will license any intellectual property rights in such information by any implication or otherwise. Sony will not assume responsibility for any problems in connection with your use of such information or for any infringement of third-party rights due to the same. It is therefore your sole legal and financial responsibility to resolve any such problems and infringement. Governing Law * This Notice shall be governed by and construed in accordance with the laws of Japan, without reference to principles of conflict of laws or choice of laws. All controversies and disputes arising out of or relating to this Notice shall be submitted to the exclusive jurisdiction of the Tokyo District Court in Japan as the court of first instance. Other Applicable Terms and Conditions * The terms and conditions in the Sony additional specifications, which will be made available to you when you order the Products, shall also be applicable to your use of the Products as well as to this specifications book. You should review those terms and conditions when you consider purchasing and/or using the Products.
-2-
ICX418AKB
Block Diagram and Pin Configuration (Top View)
VOUT SUB VDD V1 V2 V3 V4 VL
8
7
6
5
4
3
2
1
Cy
Vertical Register
Mg
Ye G Ye
Mg
Cy
Mg
Ye G Ye
Mg
Cy G Cy
Mg
Cy
G
Ye G
Cy
Mg
Ye G Note)
Horizontal Register Note) 9
NC
: Photo sensor
10
NC
11
GND
12
RD
13
RG
14
VDSUB
15
H1
16
H2
Pin Description Pin No. Symbol 1 2 3 4 5 6 7 8 V4 V3 V2 SUB V1 VL VDD VOUT Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Substrate clock Vertical register transfer clock Protective transistor bias Output circuit supply voltage Signal output Pin No. Symbol 9 10 11 12 13 14 15 16 NC NC GND RD RG VDSUB H1 H2 GND Reset drain bias Reset gate clock Substrate bias circuit supply voltage Horizontal register transfer clock Horizontal register transfer clock Description
-3-
ICX418AKB
Absolute Maximum Ratings Item Substrate clock SUB - GND Supply voltage Clock input voltage VDD, VRD, VDSUB, VOUT - GND VDD, VRD, VDSUB, VOUT - SUB V1, V2, V3, V4 - GND V1, V2, V3, V4 - SUB Ratings -0.3 to +50 -0.3 to +18 -55 to +10 -15 to +20 to +10 to +15 to +17 -17 to +17 -10 to +15 -55 to +10 -65 to +0.3 -0.3 to +30 -30 to +80 -10 to +60 Unit V V V V V V V V V V V V C C 1 Remarks
Voltage difference between vertical clock input pins Voltage difference between horizontal clock input pins H1, H2 - V4 RG - GND RG - SUB VL - SUB Pins other than GND and SUB - VL Storage temperature Operating temperature
1 +27V (Max.) when clock width < 10s, clock duty factor < 0.1%.
-4-
ICX418AKB
Bias Conditions 1 [when used in substrate bias internal generation mode] Item Output circuit supply voltage Reset drain voltage Protective transistor bias Substrate bias circuit supply voltage Substrate clock Symbol VDD VRD VL VDSUB SUB 14.55 Min. 14.55 14.55 Typ. 15.0 15.0 1 15.0 2 15.45 V Max. 15.45 15.45 Unit V V VRD = VDD Remarks
1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL power supply for the V driver should be used. (When CXD1267AN is used.) 2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD.
Bias Conditions 2 [when used in substrate bias external adjustment mode] Item Output circuit supply voltage Reset drain voltage Protective transistor bias Substrate bias circuit supply voltage Substrate voltage adjustment range Substrate voltage adjustment precision Symbol VDD VRD VL VDSUB VSUB VSUB 6.0 -3 Min. 14.55 14.55 Typ. 15.0 15.0 3 4 14.0 +3 V % 5 5 Max. 15.45 15.45 Unit V V VRD = VDD Remarks
3 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same supply voltage as the VL power supply for the V driver should be used. (When CXD1267AN is used.) 4 Connect to GND or leave open. 5 The setting value of the substrate voltage (VSUB) is indicated on the back of the image sensor by a special code. When adjusting the substrate voltage externally, adjust the substrate voltage to the indicated voltage. The adjustment precision is 3%. However, this setting value has not significance when used in substrate bias internal generation mode. VSUB code -- one character indication Code and optimal setting correspond to each other as follows. VSUB code E f 6.5 G 7.0 h 7.5 J 8.0 K 8.5 L 9.0 m N P Q R S T U V W
Optimal setting 6.0
9.5 10.0 10.5 11.0 11.5 12.0 12.5 13.0 13.5 14.0
"L" VSUB = 9.0V DC Characteristics Item Output circuit supply current Symbol IDD Min. Typ. 5.0 Max. 10.0 Unit mA Remarks
-5-
ICX418AKB
Clock Voltage Conditions Item Readout clock voltage Symbol VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 VV Vertical transfer clock voltage | VVH1 - VVH2 | VVH3 - VVH VVH4 - VVH VVHH VVHL VVLH VVLL Horizontal transfer clock voltage Reset gate clock voltage1 VH VHL VRGL VRG VRGLH - VRGLL Substrate clock voltage VSUB 4.5 4.75 -0.05 5.0 0 1 5.0 0.8 -0.25 -0.25 Min. Typ. Max. Unit V V V V Waveform diagram 1 2 2 2 2 2 2 2 2 2 2 2 3 3 4 4 4 5 Low-level coupling High-level coupling High-level coupling Low-level coupling Low-level coupling VVL = (VVL3 + VVL4)/2 VV = VVHn - VVLn (n = 1 to 4) VVH = (VVH1 + VVH2)/2 Remarks
14.55 15.0 15.45 -0.05 -0.2 0 0 0.05 0.05
-9.6 -9.0 -8.5 8.3 9.0
9.65 Vp-p 0.1 0.1 0.1 0.5 0.5 0.5 0.5 0.05 V V V V V V V V V 5.5 Vp-p V
5.25 Vp-p
23.0 24.0 25.0 Vp-p
1 Input the reset gate clock without applying a DC bias. In addition, the reset gate clock can also be driven with the following specifications.
Item Reset gate clock voltage
Symbol VRGL VRG
Min. -0.2 8.5
Typ. Max. Unit 0 9.0 0.2 V
Waveform diagram 4 4
Remarks
9.5 Vp-p
-6-
ICX418AKB
Clock Equivalent Circuit Constant Item Capacitance between vertical transfer clock and GND Capacitance between vertical transfer clocks Symbol CV1, CV3 CV2, CV4 CV12, CV34 CV23, CV41 Min. Typ. 2700 2700 820 330 100 91 47 11 680 91 100 68 Max. Unit pF pF pF pF pF pF pF pF pF Remarks
Capacitance between horizontal transfer clock CH1 and GND CH2 Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND Vertical transfer clock series resistor Vertical transfer clock ground resistor CHH CRG CSUB R1, R3 R2, R4 RGND
V1 CV12
V2
R1
R2
H1 H2 CHH
CV1 CV41
CV2 CV23
CH1
CH2
CV4 R4
RGND CV34
CV3 R3
V4
V3
Vertical transfer clock equivalent circuit
Horizontal transfer clock equivalent circuit
-7-
ICX418AKB
Drive Clock Waveform Conditions (1) Readout clock waveform
100% 90% VVT
M M 2 10% 0% tr twh tf 0V
(2) Vertical transfer clock waveform
V1 VVH1 VVHH VVH VVHL VVHL VVHH VVHL VVH3 V3 VVHH VVH
VVHH VVHL
VVL1
VVLH
VVL3
VVLH VVLL VVL
VVLL VVL
V2
V4
VVHH
VVHH
VVH VVHL
VVH
VVHH
VVHH
VVH2 VVHL
VVHL VVH4
VVHL
VVL2VVLH VVLL VVL4
VVLH
VVLL VVL
VVL
VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VV = VVHn - VVLn (n = 1 to 4)
-8-
ICX418AKB
(3) Horizontal transfer clock waveform
tr twh tf
90% VH 10% VHL
twl
(4) Reset gate clock waveform
tr
twh
tf VRGH
twl VRG VRGL + 0.5V VRGL VRGLL VRGLm H1 waveform +2.5V
Point A RG waveform VRGLH
VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the period twh, then: VRG = VRGH - VRGL Negative overshoot level during the falling edge of RG is VRGLm. (5) Substrate clock waveform
100% 90%
M VSUB 10% VSUB 0% tr twh tf M 2
-9-
ICX418AKB
Clock Switching Characteristics Item Readout clock Vertical transfer clock
Horizontal transfer clock
Symbol VT V1, V2, V3, V4 H
twh 2.3 2.5
twl 0.5
tr 0.5 15
tf
Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max.
Unit
Remarks
s During readout 250 ns 1 15 0.01 s 0.01 3 ns 0.5 s When draining charge 19 ns 2
During imaging
20 5.38
20
15 0.01
19
During H1 parallel-serial H2 conversion 11
5.38 13 51
0.01 3 0.5
Reset gate clock RG Substrate clock SUB
1.5 1.8
1 When vertical transfer clock driver CXD1267AN is used. 2 tf tr - 2ns.
Item Horizontal transfer clock
Symbol H1, H2
two Min. 16 Typ. 20 Max.
Unit Remarks ns 3
3 The overlap period for twh and twl of horizontal transfer clocks H1 and H2 is two.
- 10 -
ICX418AKB
Image Sensor Characteristics Item Sensitivity Saturation signal Smear Video signal shading Uniformity between video signal channels Dark signal Dark signal shading Flicker Y Flicker R-Y Flicker B-Y Line crawl R Line crawl G Line crawl B Line crawl W Lag Symbol S Ysat Sm SHy Sr Sb Ydt Ydt Fy Fcr Fcb Lcr Lcg Lcb Lcw Lag Min. 1040 1000 -115 -105 20 25 10 10 2 1 2 5 5 3 3 3 3 0.5 Typ. 1300 Max. Unit mV mV dB % % % % mV mV % % % % % % % % Measurement method 1 2 3 4 4 5 5 6 7 8 8 8 9 9 9 9 10 Ta = 60C Ta = 60C Zone 0 and I Zone 0 to II' Ta = 60C
(Ta = 25C) Remarks
Zone Definition of Video Signal Shading
768 (H) 14 14 12 H 8 V 10 H 8
494 (V)
Zone 0, I Zone II, II' V 10
10
Ignored region Effective pixel region
Measurement System
[A] CCD signal output CCD C.D.S AMP S/H LPF2 S/H (3dB down 1MHz) [C] Chroma signal output LPF1 (3dB down 6.3MHz) [Y] Y signal output
Note) Adjust the amplifier gain so that the gain between [A] and [Y], and between [A] and [C] equals 1. - 11 -
ICX418AKB
Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions. (when used with substrate bias external adjustment, set the substrate voltage to the value indicated on the device.) 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black level (OB) is used as the reference for the signal output, which is taken as the value of Y signal output or chroma signal output of the measurement system. Color coding of this image sensor & Composition of luminance (Y) and chroma (color difference) signals
Cy G B Cy Mg
Ye Mg Ye G
Cy G Cy Mg
Ye A1 Mg Ye A2 G
As shown in the left figure, fields are read out. The charge is mixed by pairs such as A1 and A2 in the A field. (pairs such as B in the B field) As a result, the sequence of charges output as signals from the horizontal shift register (Hreg) is, for line A1, (G + Cy), (Mg + Ye), (G + Cy), and (Mg + Ye).
Hreg Color Coding Diagram These signals are processed to form the Y signal and chroma (color difference) signal. The Y signal is formed by adding adjacent signals, and the chroma signal is formed by subtracting adjacent signals. In other words, the approximation: Y = {(G + Cy) + (Mg + Ye)} x 1/2 = 1/2 {2B + 3G + 2R} is used for the Y signal, and the approximation: R - Y = {(Mg + Ye) - (G + Cy)} = {2R - G} is used for the chroma (color difference) signal. For line A2, the signals output from Hreg in sequence are (Mg + Cy), (G + Ye), (Mg + Cy), (G + Ye). The Y signal is formed from these signals as follows: Y = {(G + Ye) + (Mg + Cy)} x 1/2 = 1/2 {2B + 3G + 2R} This is balanced since it is formed in the same way as for line A1. In a like manner, the chroma (color difference) signal is approximated as follows: - (B - Y) = {(G + Ye) - (Mg + Cy)} = - {2B - G} In other words, the chroma signal can be retrieved according to the sequence of lines from R - Y and - (B - Y) in alternation. This is also true for the B field. - 12 -
ICX418AKB
Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F5.6. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the Y signal (Ys) at the center of the screen and substitute the value into the following formula. S = Ys x 250 [mV] 60
2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with average value of the Y signal output, 200mV, measure the minimum value of the Y signal. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with average value of the Y signal output, 200mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value YSm [mV] of the Y signal output and substitute the value into the following formula. Sm = 20 x log YSm x 1 x 500 200 1 10 [dB] (1/10V method conversion value)
4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the Y signal output is 200mV. Then measure the maximum (Ymax [mV]) and minimum (Ymin [mV]) values of the Y signal and substitute the values into the following formula. SHy = (Ymax - Ymin)/200 x 100 [%] 5. Uniformity between video signal channels Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal output is 200mV, and then measure the maximum (Crmax, Cbmax [mV]) and minimum (Crmin, Cbmin [mV]) values of the R - Y and B - Y channels of the chroma signal and substitute the values into the following formula. Sr = | (Crmax - Crmin)/200 | x 100 [%] Sb = | (Cbmax - Cbmin)/200 | x 100 [%] 6. Dark signal Measure the average value of the Y signal output (Ydt [mV]) with the device ambient temperature 60C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. - 13 -
ICX418AKB
7. Dark signal shading After measuring 6, measure the maximum (Ydmax [mV]) and minimum (Ydmin [mV]) values of the dark signal output and substitute the values into the following formula. Ydt = Ydmax - Ydmin [mV] 8. Flicker 1) Fy Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal output is 200mV, and then measure the difference in the signal level between fields (Yf [mV]). Then substitute the value into the following formula. Fy = (Yf/200) x 100 [%] 2) Fcr, Fcb Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal output is 200mV, insert an R or B filter, and then measure both the difference in the signal level between fields of the chroma signal (Cr, Cb) as well as the average value of the chroma signal output (CAr, CAb). Substitute the values into the following formula. Fci = (Ci/CAi) x 100 [%] (i = r, b) 9. Line crawls Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the Y signal output is 200mV, and then insert a white subject and R, G, and B filters and measure the difference between Y signal lines for the same field (Ylw, Ylr, Ylg, Ylb [mV]). Substitute the values into the following formula. Lci = (Yli/200) x 100 [%] (i = w, r, g, b) 10. Lag Adjust the Y signal output value generated by strobe light to 200mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Ylag). Substitute the value into the following formula. Lag = (Ylag/200) x 100 [%]
FLD
V1
Light Strobe light timing
Y signal output 200mV Output
Ylag (lag)
- 14 -
Drive Circuit 1 (substrate bias internal generation mode)
15V
1 19 18 1/35V 1 17 16 CXD1267AN 15 14 22/16V 13 12 11 1M 100k
20
2
3
XSUB
4
XV2
5
-9V 3.3/16V
XV1
6
XSG1
7
XV3
8
XSG2
9
XV4
10
22/20V 1
V4 V3 V2 SUB
0.01 2 3 4 5
V1
VL
VDD
ICX418 (BOTTOM VIEW)
H2 H1 RG RD GND NC VDSUB NC
16
15
14
13
12
11
10
H1 0.01
H2
100 [A] CCD OUT 0.01 3.9k
ICX418AKB
RG
VOUT
- 15 -
6
7
8
3.3/20V
9
Drive Circuit 2 (substrate bias external adjustment mode)
15V 0.1 15k 47k 56k 1/35V 1/35V 100k 27k 0.1 0.1 -9V 3.3/16V 22/16V 39k 15k 1/35V 20 19 18 17 16 CXD1267AN 15 14 13 12 11 3.3/20V 1 2 3 4 5 6 7 8 0.01 1M 270k
1
2
3
XSUB
4
XV2
5
XV1
6
XSG1
7
XV3
8
XSG2
9
XV4
10
V4
V3
V2
V1
VL
SUB
VDD
ICX418 (BOTTOM VIEW)
VDSUB
H2
H1
RG
RD
GND
NC
16 15 14 13 12 11 10 0.01 100
H1
H2
NC
9
VOUT
- 16 -
0.01
22/20V
3.9k
[A] CCD OUT
ICX418AKB
RG
ICX418AKB
Spectral Sensitivity Characteristics (Excludes lens characteristics and light source characteristics)
1.0 Cy 0.8 G Ye
Relative Response
0.6
0.4
Mg
0.2
0 400
450
500
550 Wave Length [nm]
600
650
700
Sensor Readout Clock Timing Chart
V1 V2 Odd Field V3 V4 33.5 1.6 0.2
2.5
2.5 2.5 2.5
V1 V2 Even Field V3 V4 Unit: s
- 17 -
Drive Timing Chart (Vertical Sync)
FLD
VD
BLK
HD
10
15
20
520
525 1 2 3 4 5
- 18 -
246 135 246 135 494 493
V1
V2
V3
V4 135 246
CCD OUT
493 494
260
265
270
275
135 246
280
ICX418AKB
Drive Timing Chart (Horizontal Sync)
HD
BLK
H1
1 2 3 5 10 10 30 40 20 22 1 2 3 1 2 3 20
H2
760
- 19 -
RG
V1
V2
V3
V4
SUB
768 1 2 3 5
10
20
ICX418AKB
ICX418AKB
Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operations as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Do not expose to strong light (sun rays) for long periods, as color filters will be discolored. When high luminous objects are imaged with the exposure level control by the electronic-iris, the luminance of the image-plane may become excessive and discolor of the color filter will possibly be accelerated. In such a case, it is advisable that taking-lens with the automatic-iris and closing of the shutter during the power-off mode should be properly arranged. For continuous using under cruel condition exceeding the normal using condition, consult our company. 5) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. 6) CCD image sensors are precise optical equipment that should not be subject to too much mechanical shocks.
- 20 -
Package Outline
Unit: mm
16 pin DIP (300mil)
3.29 0.3 A
1.84
B
0.
9 9 16
3
2.54 4.0
C
.2 13 16
~
~
~
1
12.0 0.15
1.5
1st. pin Index 12.0 0.15 12.35 0.3
6.175
1. "A" is the center of the effective image area. 2. The point "B" of the package is the horizontal reference. The point "B'" of the package is the vertical reference.
1.84
4.0 0.2
1.0
- 21 -
1.5 1.5 0.7
B'
3. The bottom "C" of the package is the height reference. 4. The center of the effective image area relative to the center of the package () is (H, V) = (0, 0) 0.15mm. 5. The rotation angle of the effective image area relative to H and V is 1. 6. The height from the bottom "C" to the effective image area is 1.41 0.15mm.
~
~
0.6 0.3
1.27
7. The tilt of the effective image area relative to the bottom "C" is less than 60m. 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5.
0.3
M
PACKAGE STRUCTURE
PACKAGE MATERIAL
Ceramic
Center of the package : The center is halfway between two pairs of opposite sides, as measured from "B", "B'".
LEAD TREATMENT
GOLD PLATING
LEAD MATERIAL
42 ALLOY
PACKAGE MASS
0.90g
ICX418AKB
Sony Corporation
DRAWING NUMBER
AS-B4-01(E)
0.25
1 8
H 8
6.175
V
12.35 0.3
7.62
4.0


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